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我在我的 VHDL 代码中编写了 2 个状态机。模拟工作正常，但代码没有合成。任何帮助，将不胜感激。这是我的代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.NUMERIC_STD.ALL;

entity pulse_width is
Port (  clk : in STD_LOGIC;
            timer2:in std_logic;
            input: in STD_LOGIC;
            result: inout STD_LOGIC_VECTOR (15 downto 0);
            SEL_LINE: IN STD_LOGIC_VECTOR(5 DOWNTO 0);
            data_out: out STD_LOGIC_VECTOR (23 downto 0):=x"000000");
end pulse_width;

architecture Behavioral of pulse_width is
    TYPE count_states is (s0,s0_dash,s1,s2,s3,s1_dash);
    SIGNAL current_state, next_state : count_states := s0 ;
    TYPE write_states is (ws0,ws0_dash,ws1,ws2,ws3,ws4);
    SIGNAL current_state1, next_state1 : write_states := ws0 ;
    TYPE index_array is ARRAY(integer range 0 to 65535) of std_logic_vector(15 downto 0);
    SIGNAL mem: index_array;
    SIGNAL count: std_logic_vector(15 downto 0):=x"0000";
    SHARED VARIABLE j: integer:=0;
    SHARED VARIABLE a,i: integer:=1;
    SIGNAL flag,push_data,push_first,push_final,push_pulses,rw_first,rw_end: std_logic:='0';
    SIGNAL y_clk_input ,y_clk_timer2, enable_count: std_logic:='0';
    SIGNAL first,final: std_logic_vector(15 downto 0):= x"0001";

begin
-- Pulse width count

process (clk)
begin
    if rising_edge(clk) then
        current_state<=next_state;
        current_state1<=next_state1;
    end if;
end process;


process(input,SEL_LINE,current_state)
begin

------------------------------------------------------------------------
    case current_state is
    when s0 => 
        if(input='1') then
            next_state<=s1;
        else
            next_state<=s0;
        end if;
    when s1 =>
        flag<='0';
        if input='1' then
            count <= count+ x"0001";
            next_state<=s1_dash;
        else
            next_state<=s2;
        end if;         
    when s1_dash =>
        if input='1' then
            count <= count+ x"0001";
            next_state<=s1;
        else
            next_state<=s2;
        end if;         
    when s2 =>
            result <= count;
            next_state<=s3;
    when s3=>
            count <= x"0000";
            next_state<=s0;
            enable_count<='0';
    when others =>
        next_state<=s0;
    end case;

--------------------------------------------------------------------------
    case current_state1 is
    when ws0 =>
        if  (result>x"0000") then
        next_state1<=ws1;
        else
        next_state1<=ws0_dash;
        end if;
    when ws0_dash =>
        if  (result>x"0000") then
        next_state1<=ws1;
        else
        next_state1<=ws0;
        end if;
    when ws1=>
        if rw_first='1' and rw_end='1' then
        next_state1<=ws0;
        else
            mem(a) <= result;
            a:=a+1;
            final<=final+x"0001";
            next_state1<=ws2;
        end if;
    when ws2 =>
            next_state1<=ws0;
            result<=x"0000";
    when others  =>
        next_state1<=ws0;
    end case;
end process;

我最终需要实现三个状态机。

4

2 回答 2

0

您尝试在异步状态逻辑中执行的数学运算未注册并且不会很好地综合。您需要重新安排您的状态逻辑，以便声明如下：

count <= count+ x"0001";
...
final<=final+x"0001";

...在异步循环中是同步的而不是“自由运行”。

于 2013-03-04T12:58:47.263 回答
0

问题是您在一个组合过程中读取和写入相同的信号。

  • 要么将所有内容放在一个时钟（同步）过程中
  • 或者：使用显式寄存器：count_next <= count + x"0001";

与您的错误无关，但仍然值得关注：

您有大量未使用的信号和共享变量： push_data,push_first,push_final,push_pulses, y_clk_input ,y_clk_timer2, first, i,j 这会让任何试图阅读您的代码的人感到困惑。1

包 STD_LOGIC_arith 和 STD_LOGIC_unsigned 已弃用

于 2013-03-04T15:47:07.363 回答