verilog - Oring of outputs in Verilog

Question

I have generated 15 modules using generate having m[0:14] outputs. I want to or them together. Will this work?

if (m == 1)begin
result = 1;
end

Or, if not, then what is the optimum way to do it.

Answer 1

您正在寻找 verilog 中的归约操作。

( |m ) = m[1] | m[2] | m[3] ...

http://www.ee.ed.ac.uk/~gerard/Teach/Verilog/manual/Operators/reduction.html

Answer 2

assign result = |m;应该管用。The|是一元归约 or，它or是 m 的所有位在一起。

您所拥有的将不起作用，因为它将与 比较m，'d1如果 m 是 ，这将是正确的000000000000001。

Answer 3

请注意，这也将起作用：

if (m) result = 1;

由于|m被隐式执行以将值转换为布尔值