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我是verilog的业余爱好者。我正在尝试调用模块分隔符。但我在综合中遇到错误，例如“对向量 reg 'qtnt' 的引用不是合法的净左值”。我曾尝试使用电线作为输入，但是当我尝试为它们分配值时，收到一条错误消息。请帮忙

module euclid_mul(
  input[9:0] p0,p1,q0,
  input[19:0] tot,
  input clk,
  output reg [20:0] p2,
  output reg out_en,o1,o2
);
reg[20:0] dvr,dvd,qtnt,rem;
reg[9:0] ph;
reg[20:0] mul,res;
reg enable,f1;

initial f1=0;
initial enable=0;

divider div2(dvd,dvr,enable,qtnt,rem,f1);   

always @ (negedge clk)
  begin 
    if(f1==0) begin
      mul=q0*p1;
      ph=p0;
      res={11'b00000000000,ph[9:0]}-mul;
      if(res[20])
        begin
          o1=1;
          dvd=-res;
        end
      else
        dvd=res;
        o2=1;
        dvr=tot;
        enable=1;
      end
    end

    always @(posedge f1)
      begin
        if(res[20]) 
          begin 
            p2=tot-rem;
            out_en=1;
          end
        else
          begin
            p2=rem;
            out_en=1;
          end
        end
      endmodule
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1 回答 1

1

You may get more response if you formatted the code so that it was easier to read. Something like the following:

I have also pointed out a section where I think you are missing a begin and end statement. Also inside clocked sections you often want to use nonblocking assignments <=.

Since you have not provided the divider module, I would prefer to see ports named rather than specified in order, it might help us to know what it is likely to do, even better label it with its direction and width.

module euclid_mul(
  input       [9:0] p0,p1,q0,
  input      [19:0] tot,
  input             clk,
  output reg [20:0] p2,
  output reg        out_en,o1,o2
);
reg [20:0] dvr,dvd,qtnt,rem;
reg  [9:0] ph;
reg [20:0] mul,res;
reg        enable,f1;

initial begin
  f1     = 0;
  enable = 0;
end

divider div2(dvd,dvr,enable,qtnt,rem,f1);   
// My prefered style to help us understand conectivity.
//divider
//  divider_i0(
//    .divisor( dvd ), //input  [20:0]
//    .result ( res )  //output [20:0]
//);


always @ (negedge clk) begin 
  if(f1==0) begin
    mul = q0*p1;
    ph  = p0;
    res = {11'b00000000000,ph[9:0]}-mul;
    if ( res[20] ) begin
      o1  = 1;
      dvd = -res;
    end
    else begin //There was a missing begin
      dvd   = res;
      o2    = 1;
      dvr   = tot;
     enable = 1;
    end //Missing End
  end
end

always @(posedge f1) begin
  if(res[20]) begin 
    p2     = tot-rem;
    out_en = 1;
  end
  else begin
    p2     = rem;
    out_en = 1;
  end
end
endmodule

Inputs can be regs and driven from inside always or initial blocks, or wires driven from a single assign or another modules output.

Outputs should always be connected to wires, the module drives them.

于 2013-02-06T16:43:06.750 回答