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我在构建模块链时遇到了麻烦。我可以手动连接模型列出所有模块，但需要更简洁的表示。以下代码已尝试但不起作用？如何更正代码？

module network(
    input signed [31:0] xi,
    output signed [31:0] yo,
    input clk,
    input reset
    );

    wire signed [31:0] x0, x1, x2, y0, y1, y2, xo;
    wire [3:1] t;
    //working code for chain of pe
//   pe u0(xi, x0, 0, y0, clk, reset);  
//   pe u1(x0, x1, y0, y1, clk, reset);
//   pe u2(x1, x2, y1, y2, clk, reset);
//   pe u3(x2, xo, y2, yo, clk, reset);
    //chain of array not working! how!
    pe p[1:4] ((xi,t), (t, x), (0, t), (t,yo),clk,reset); <- want to improve
endmodule

这里，pe（输入，输出，输入，输出，时钟，复位）。

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1 回答 1

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试试这个。它应该适用于所有版本的 Verilog。在这种情况下，参数 PE_NUM 必须是值为 2 或更大的 int。如果需要 1 pe 实例，则必须使用生成块，这需要 Verilog-2001 或 SystemVerilog。当 PE_NUM 变大时（例如 2**16），某些模拟器可能会遇到内存限制。

/*All Verilog*/
module network(
        input signed [31:0] xi,
        output signed [31:0] yo,
        input clk,
        input reset
        );
    parameter PE_NUM = 4; // limitation PE_NUM must be greater then 1
    wire signed [31:0] xo;
    wire signed [0:PE_NUM-2] [31:0] xN;
    wire signed [0:PE_NUM-2] [31:0] yN;
    pe p[0:PE_NUM-1] ({xi,xN}, {xN,xo}, {32'b0,yN}, {yN,yo}, clk,reset);
endmodule

以下是使用生成的示例：

/*Verilog-2001 or SystemVerilog*/
module network(
        input signed [31:0] xi,
        output signed [31:0] yo,
        input clk,
        input reset
        );
    parameter PE_NUM = 4; // no limitation
    wire signed [31:0] xo;
    generate
        if(PE_NUM <2) begin
            pe p (xi, xo, 32'b0, yo, clk,reset);
        end
        else begin
            wire signed [0:PE_NUM-2] [31:0] xN;
            wire signed [0:PE_NUM-2] [31:0] yN;
            pe p[0:PE_NUM-1] ({xi,xN}, {xN,xo}, {32'b0,yN}, {yN,yo}, clk,reset);
        end
    endgenerate
endmodule
于 2013-01-09T01:15:51.647 回答