system-verilog - 错误 (10170)：alarm_clock.v(133) 附近文本“和”处的 Verilog HDL 语法错误；期待“）”

Question

我不断收到这个错误，我尝试了各种方法来修复它，但它对我没有帮助。

我希望有人能在这方面帮助我。

有问题的代码片段如下：

if((HR == AHR) and (MIN == AMIN)) To be exact.

always @ (posedge CLK)
begin
case(state)
NORMAL: begin
        DHR <= HR;
        DMIN <= MIN;
        if(ALON)
            begin
            AENABLED <= 1;

            if((HR == AHR) and (MIN == AMIN))
                begin
                ALARM <= 1;
                if(SNOOZE) // we assume that SNOOZE is to be operated only when the Alarm is ON!
                    begin
                    AMIN <= AMIN + 2;
                    if(AMIN == 60)
                        begin
                        AMIN <= 0;
                        AHR <= AHR + 1;
                            if(AHR == 24)
                                AHR <= 0;
                        end
                    else if(AMIN == 61) // since AMIN is incremented by 2 it can either be 60 or 61 depending on previous alarm time
                        begin
                        AMIN <= 1;
                        AHR <= AHR + 1;
                            if(AHR == 24)
                            AHR <= 0;
                        end
                    end
                end
            end

Answer 1

and不是verilog！试试&&吧。