binary - 在 Verilog 中将数字变为负数

Question

当你有一个binary number,A = 5'b00100并且你得到它的否定version时, B.

 reg signed [4:0] A, B;
 B = -A;

这是做什么的？

Answer 1

它将创建数字的二进制补码：翻转位并加一！

• https://en.wikipedia.org/wiki/Two%27s_complement

Answer 2

in the above case if both A/B are declared as 'signed', then the simple logic of B = -A should work and i tried in a simple case and it works. Verilog already does everything in 2's complement.