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我正在尝试使用 veriwell 模拟以下电路。但是，模拟结果给了我每个网络的值作为 x。由于电路没有任何反向循环，我猜每个网络都应该有 1 或 0 信号。

module dff (CK,Q,D);
input CK,D;
output Q;

  wire NM,NCK;
  wire NQ,M;

  nmos N7 (M,D,NCK);
  not P3 (NM,M);
  nmos N9 (NQ,NM,CK);
  not P5 (Q,NQ);
  not P1 (NCK,CK);

endmodule

module s27(clk, in1, in2, GO, HO, AO, BO, CO, DO, EO, FO, a1, a2, a3, a4, o1, o2);
input clk, in1, in2;
output GO, HO, AO, BO, CO, DO, EO, FO, a1, a2, a3, a4, o1, o2; 
wire AO, BO, CO, DO, EO, FO; 
wire a1, a2, a3, a4; 
wire o1, o2; 

  dff A(clk,AO,in1);
  dff B(clk,BO,in2);
  dff C(clk,CO,o1);
  dff D(clk,DO,a1);
  dff E(clk,EO,a2);
  dff F(clk,FO,o2);
  dff G(clk,GO,a3);
  dff H(clk,HO,a4);

  and AND2_1 (a1, AO, CO);
  and AND2_2 (a2, CO, BO);
  and AND2_3 (a3, AO, FO);
  and AND2_4 (a4, FO, BO);

  or OR2_1(o1, AO, BO);
  or OR2_2(o2, DO, EO);
endmodule

我正在使用以下测试台（使用脚本生成）：

  `timescale 1ns/1ps

module testbench;

parameter sOutFileName = "beSimOut.txt";
parameter nVectorWidth = 3;
parameter nVectorSpace = 1000;
parameter nSimCycle = 10;

/* simulation memory */
reg [nVectorWidth - 1:0] mSimMemory [nVectorSpace - 1:0];

/* simulation vector */
reg [nVectorWidth - 1:0] vSimVector;

/* bench variables */
integer nOutFile, nIndex;

/* connection variable declarations */
wire clk, in1, in2, G0, H0, A0, B0, C0, D0, E0, F0, a1, a2, a3, a4, o1, o2;
/* drive inputs */
assign clk = vSimVector[2];
assign in1 = vSimVector[1];
assign in2 = vSimVector[0];

/* simulation memory population routine */
task populateSimulationMemory;
begin
    for (nIndex = 0; nIndex < nVectorSpace; nIndex = nIndex + 1)
        mSimMemory[nIndex] = { $random };
end
endtask

/* simulation */
initial
begin
    /* start monitoring */
    $monitor($time, ": clk = %b, in1 = %b, in2 = %b, GO = %b, HO = %b, AO = %b, BO = %b, CO = %b, DO = %b, EO = %b, FO = %b, a1 = %b, a2 = %b, a3 = %b, a4 = %b, o1 = %b, o2 = %b", clk, in1, in2, GO, HO, AO, BO, CO, DO, EO, FO, a1, a2, a3, a4, o1, o2);

    /* populate simulation memory */
    populateSimulationMemory;

    /* open dump file */
    nOutFile = $fopen(sOutFileName);
    if (nOutFile == 0)
    begin
        $display("Can't open %s file for dumping. Exiting ...", sOutFileName);
        $finish;
    end

    /* simulate inputs */
    for (nIndex = 0; nIndex < nVectorSpace; nIndex = nIndex + 1)
        #nSimCycle vSimVector = mSimMemory[nIndex];

    #1 $fclose(nOutFile);
    nOutFile = 0;
    $finish;
end

/* instantiation */
s27 inst (.clk(clk), .in1(in1), .in2(in2), .GO(GO), .HO(HO), .AO(AO), .BO(BO), .CO(CO), .DO(DO), .EO(EO), .FO(FO), .a1(a1), .a2(a2), .a3(a3), .a4(a4), .o1(o1), .o2(o2));

/* dump */
always @(clk or in1 or in2 or GO or HO or AO or BO or CO or DO or EO or FO or a1 or a2 or a3 or a4 or o1 or o2)
    if (nOutFile != 0)
        $fdisplay(nOutFile, $time, ": clk = %b, in1 = %b, in2 = %b, GO = %b, HO = %b, AO = %b, BO = %b, CO = %b, DO = %b, EO = %b, FO = %b, a1 = %b, a2 = %b, a3 = %b, a4 = %b, o1 = %b, o2 = %b", clk, in1, in2, GO, HO, AO, BO, CO, DO, EO, FO, a1, a2, a3, a4, o1, o2);

endmodule

关于为什么我没有得到正确输出的任何想法？

提前致谢。

4

2 回答 2

2

dff 未正确建模。使用当前的 dff，当 CK 为高电平时，M 将浮动（高 Z）。

dff 应如下所示：

not N1 (NCK,CK);
cmos C1 (M,D,NCK,CK);
cmos C2 (M,NNM,CK,NCK);
not N2 (NM,M);
not N3 (NNM,NM);
cmos C3 (NNQ,NNM,CK,NCK);
cmos C4 (NNQ,Q,NCK,CK);
not N3 (NQ,NNQ);
not N4 (Q,NQ);

或作为与非门：

nand DN1 (NM,D,CK);
nand DN2 (M,NM,CK);
nand DN3 (Q,NQ,NM);
nand ND4 (QN,Q,M);

或作为行为：

always @(posedge CK)
  Q <= D;
于 2013-01-09T21:54:31.917 回答
1

当我尝试使用 VCS 模拟器编译代码时，出现编译错误：

尚未声明标识符“GO”。如果此错误不是预期的，请检查您是否已将 `default_nettype 设置为 none。

在您的测试台模块中，您声明了一条线G0（数字零），然后使用GO（大写字母 O）。您应该将零更改为字母 O。

我认为这不会完全解决您的问题，但这太复杂了，无法放入评论中。

于 2012-11-19T20:21:57.620 回答