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我想用 Quartus II 创建一个项目，它的功能是根据代码启用三个不同的 LED。当您输入代码时，第一个 LED 将亮起。根据输入的代码，第二个或第三个将打开。我的问题是，当代码正确时，我希望第二个 LED 亮 3 秒，如果不正确，第三个 LED 将在 2 秒内亮。如果你能帮助我，那就太好了。

谢谢！

注：led 被声明为逻辑向量，代码的编号被声明为从 0 到 7 的中断。

代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY programa IS
PORT
(
interrup : in Std_Logic_Vector (7 downto 0);
clk, rst: in Std_Logic;
led : out Std_Logic_Vector (2 downto 0)
);
END programa;
ARCHITECTURE arch_programa OF programa IS
    type state is (zero, one, two, three, four, five, six);
    signal pr_state, nx_state : state;
    signal A : Std_Logic_Vector (3 downto 0);
BEGIN
    process(interrup, pr_state)
    begin
        case pr_state is
            when zero =>
                led <= "100";
                A(0) <= interrup(7);
                nx_state <= one;
            when one =>
                led <= "100";
                A(1) <= interrup(6);
                nx_state <= two;
            when two =>
                led <= "100";
                A(2) <= interrup(5);
                nx_state <= three;
            when three =>
                led <= "100";
                A(3) <= interrup(3);
                nx_state <= four;
            when four =>
                led <= "100";
                if(A = "1111") then nx_state <= five;
                else nx_state <= six;
                end if;
            when five =>
                led <= "010";
                nx_state <=zero;
            when six =>
                led <= "001";
                nx_state <=zero;
            end case;
    end process;

    process(rst,clk)
    begin
        if(rst='1') then
            pr_state <= zero;
        elsif (clk'event and clk = '1') then
            pr_state <= nx_state;
        end if;         
    end process;

end arch_programa;
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2 回答 2

1

至于第一个问题，您需要计算 3 或 2 秒的时钟脉冲，因此您需要知道时钟频率。例如，当您打开 LED 时启动计数器，当您计算出正确的脉冲数时关闭 LED 和计数器。从该值开始倒数并在计数器达到零时停止通常更容易。

至于第二个，按钮必须通过输入端口连接，您可以将其用作其中一个进程的输入。

于 2012-11-15T19:43:29.183 回答
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可能有很多方法可以解决这个问题，但是在不更改代码的情况下，这里有一个（注意，未完全测试）。

  • 给每个状态一个取决于时钟速率的计数输出。
  • 建立一个足以容纳最大计数的计数器寄存器。
  • 减少每个时钟的计数，当它为零时重新加载。
  • 重载值来自新状态。
  • 在零之前的最后一个计数上切换状态。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY programa IS
PORT
(
    interrup : in Std_Logic_Vector (7 downto 0);
    clk, rst: in Std_Logic;
    led : out Std_Logic_Vector (2 downto 0)
);
END programa;           

ARCHITECTURE arch_programa OF programa IS
    type state is (zero, one, two, three, four, five, six);
    signal pr_state, nx_state : state;
    signal A : Std_Logic_Vector (3 downto 0);
    signal count,pr_count:integer;  --NOTE: Synthisizing integers is very unpredictable, should use unsigned    
BEGIN
    assign_counts:process(pr_state)
    begin
         --no idea what states need what delay, this is just an example
         case pr_state is
             when zero | one | two => 
                  pr_count<=10;
             when four =>
                  pr_count<=20;
             when others =>
                  pr_count<=50;
         end case;
    end process;

    process(interrup, pr_state)
    begin
        case pr_state is
            when zero =>
                led <= "100";
                A(0) <= interrup(7);
                nx_state <= one;
            when one =>
                led <= "100";
                A(1) <= interrup(6);
                nx_state <= two;
            when two =>
                led <= "100";
                A(2) <= interrup(5);
                nx_state <= three;
            when three =>
                led <= "100";
                A(3) <= interrup(3);
                nx_state <= four;
            when four =>
                led <= "100";
                if(A = "1111") then nx_state <= five;
                else nx_state <= six;
                end if;
            when five =>
                led <= "010";
                nx_state <=zero;
            when six =>
                led <= "001";
                nx_state <=zero;
            end case;
    end process;

    process(rst,clk)
    begin
        if(rst='1') then
            pr_state <= zero;
            count<=pr_count;
        elsif (clk'event and clk = '1') then
            if count=0 then
                count<=pr_count;
            elsif count=1 then
                pr_state <= nx_state;
                count<=count-1;
            else
                count<=count-1;
            end if;
        end if;         
    end process;        
end architecture;

--Test bench
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity bench is
end bench;


architecture bench of bench is   

component programa IS
  PORT (
    interrup : in Std_Logic_Vector (7 downto 0);
    clk, rst: in Std_Logic;
    led : out Std_Logic_Vector (2 downto 0));
END component;  

signal clk:std_logic:='1';   
signal interrup:std_logic_vector (7 downto 0);
signal rst:std_logic;
constant freq:real:=1.0e6;

begin   

    do_reset:process
    begin 
        rst<='1';
        wait for 10 us;
        rst<='0';
        wait;
    end process;

    clk<=not clk after 0.5 sec / freq;

    UUT:programa port map (
      interrup => interrup,
      clk => clk,
      rst => rst);


end architecture;
于 2012-11-16T13:53:41.963 回答