我正在研究嵌入式系统中的内存层次结构这一主题。在某些嵌入式 SOC 设备上，芯片上提供了专用 SRAM。我的问题是：
为什么 SOC 嵌入式 SRAM 通常缓存与主存系统不一致？
因此，通常 SRAM 被映射到非缓存地址空间。
我知道 SRAM 的内容取决于应用程序，并且通常一个特定的链接器部分将特定的数据结构映射到 SRAM，以减少对这些数据的访问时间。例如，可以将中断向量表放入 SRAM 以减少访问时间并强制执行确定性中断处理。缓存 SRAM 会使 SRAM 访问不确定，因为可能发生缓存未命中。
无论如何，我不明白这是否与 SRAM 不缓存一致的原因有关。
谢谢。
On die memory us usually very fast. Depending on how small/embedded you are asking about the cache and the on chip ram are the same speed so it would be silly to slow down the on die sram by adding extra cycles and widening the accesses by putting sram in front of it. Those systems often have on chip flash as well and that does desire a cache or some sort of buffering to speed up execution and in that case you would see the cache in front of the flash. To use the cache in front of sram for data accesses you would need some sort of memmory management, more stuff to take space on die and more stuff to slow things down. A simple solution is to for example in the chip design declare everything with the msbit of the address set uncached and put your peripherals there and everything with the msbit not set cachable if the cache is enabled and put your ram and flash there.
If you have on chip and off chip memory that off chip memory space might want a cache and probably like the upper address bit or bits solution have only the off chip memory being cached (since it is likely slower).
In order to boot the vector table needs to be in flash, in general. Some systems let you after boot switch what memory responds to that address space, branch to another address space for the flash, flip a control bit and now there is ram at the ivt, then you copy or create your new vector table in ram. The flash memory that holds the ivt on boot is not necessarily non-deterministic, I would lean toward it being very deterministic, as deterministic as the on chip ram. Perhaps a few clocks slower per access. Your interrupt and any other execution performance is often more determined by your language and compiler than the system.
Perhaps you should specify the exact system or systems you are confused about.