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我编写了以下 VHDL 代码，它是快速加法器的组件。快速加法器由一个连接到加法器的 8by8 寄存器组成，加法器的代码如下。我怎样才能消除使用 inout Read_Adress。我希望 Read_Adress 出 std_logic_vector 而不是 inout？

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

Entity Adder is
port(
        Clock_50_MHZ :in std_logic;
        En :in std_logic;
        Data_Registerfile : in std_logic_vector(7 downto 0);
        Read_Address: inout std_logic_vector(2 downto 0) := "000";
            Output : out std_logic_vector(11 downto 0)
 );
 end Adder;

 Architecture arch of Adder is
 Signal result : unsigned (11 downto 0):="000000000000";
 Signal regData: std_logic_vector(7 downto 0);

 Begin
 regData <= Data_Registerfile;
 Process(Clock_50_MHZ)
Begin
if rising_edge(Clock_50_MHZ)  then
    if (En = '1') then
        if(Read_Address = "000") then
            result <= "000000000000" + unsigned(regData);
            Read_Address <= Read_Address + 1;
        elsif(Read_Address = "111") then
            Output <= std_logic_vector( result + unsigned(regData) );
            Read_Address <= "000";
        else
            result <= result + unsigned(regData);
            Read_Address <= Read_Address + 1;
        end if;
    end if;
end if;
 End Process;
end arch;
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2 回答 2

4

这是 VHDL 中一个典型的不便之处：您不能将out端口用作信号（如果您习惯了 Verilog，您经常会发现自己想要这样做）。

我知道的最好方法是创建一个额外的虚拟信号：

signal Read_Address_tmp : std_logic_vector(2 downto 0) := "000";

用它做计算：

     Process(Clock_50_MHZ)
 Begin
 if rising_edge(Clock_50_MHZ)  then
     if (En = '1') then
         if(Read_Address_tmp = "000") then
             result <= "000000000000" + unsigned(regData);
             Read_Address_tmp <= Read_Address_tmp + 1;
         elsif(Read_Address_tmp = "111") then
             Output <= std_logic_vector( result + unsigned(regData) );
             Read_Address_tmp <= "000";
         else
             result <= result + unsigned(regData);
             Read_Address_tmp <= Read_Address_tmp + 1;
         end if;
     end if;
 end if;
  End Process;

然后将其链接到您的输出：

Read_Address <= Read_Address_tmp;
于 2012-10-19T02:05:37.833 回答
0

从历史上看，欧文的回答是通常的方式。

The "new" VHDL 2008 allows reading of out-mode ports now. If your tools don't support it, log a bug with the vendor. See the bottom of this page from "VHDL 2008 - just the new stuff"

http://books.google.co.uk/books?id=ETxLguPMEY0C&pg=PA163&lpg=PA163#v=onepage&q&f=false

于 2012-10-19T12:13:56.950 回答