又是我！首先我想说我几天前学习了VHDL，而且我还是个新手，所以我容易犯愚蠢的错误。任何建议都会很棒。我为可用作内存控制器的模块编写了 VHDL 代码。
这是我的代码：
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memory_controller is
port(clk: in std_logic;
reset: in std_logic;
bus_id: in std_logic_vector(7 downto 0);
read_write, burst: in std_logic;
ready: in std_logic;
oe, we: out std_logic;
addr_1, addr_2: out std_logic_vector(7 downto 0)
);
end memory_controller;
architecture behavioral of memory_controller is
type statetype is (idle, decision, wr, rd1, rd2, rd3, rd4);
signal present_state, next_state : statetype;
signal addr_int : integer range 0 to (2**addr_1'length)-1;
begin
Synch_reset: process(clk)
begin
if (rising_edge(clk)) then
if (reset ='0') then
present_state <= next_state;
else
present_state <= idle;
end if;
end if;
end process;
decision_logic: process(present_state, read_write, ready, burst)
begin
case present_state is
when idle =>
oe <= '0'; we <= '0'; addr_int <= 0;
addr_1 <= std_logic_vector(to_unsigned(addr_int, addr_1'length));
addr_2 <= std_logic_vector(to_unsigned(addr_int, addr_2'length));
if(bus_id = "11110011") then
next_state <= decision;
else
next_state <= idle;
end if;
when decision =>
if (read_write = '1') then
next_state <= rd1;
else
next_state <= wr;
end if;
when wr =>
we <= '1';
if (ready = '1') then
next_state <= idle;
else
next_state <= wr;
end if;
when rd1 =>
oe <= '1';
if(ready = '0') then
next_state <= rd1;
else
if(burst = '0') then
next_state <= idle;
else
next_state <= rd2;
addr_int <= addr_int + 1;
addr_1 <= std_logic_vector(to_unsigned(addr_int, addr_1'length));
addr_2 <= std_logic_vector(to_unsigned(addr_int, addr_2'length));
end if;
end if;
when rd2 =>
oe <= '1';
if(ready = '1') then
next_state <= rd3;
addr_int <= addr_int + 1;
addr_1 <= std_logic_vector(to_unsigned(addr_int, addr_1'length));
addr_2 <= std_logic_vector(to_unsigned(addr_int, addr_2'length));
else
next_state <= rd2;
end if;
when rd3 =>
oe <= '1';
if(ready = '1') then
next_state <= rd4;
addr_int <= addr_int + 1;
addr_1 <= std_logic_vector(to_unsigned(addr_int, addr_1'length));
addr_2 <= std_logic_vector(to_unsigned(addr_int, addr_2'length));
else
next_state <= rd3;
end if;
when rd4 =>
oe <= '1';
if(ready = '1') then
next_state <= idle;
else
next_state <= rd4;
end if;
end case;
end process;
end behavioral;
这是我的测试台：
Library IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity memory_controller_tb is
end memory_controller_tb;
architecture test of memory_controller_tb is
component memory_controller
port(clk: in std_logic;
reset: in std_logic;
bus_id: in std_logic_vector(7 downto 0);
read_write, burst: in std_logic;
ready: in std_logic;
oe, we: out std_logic;
addr_1, addr_2: out std_logic_vector(7 downto 0)
);
end component;
signal clk: std_logic;
signal reset: std_logic;
signal read_write, burst, oe, we: std_logic;
signal addr_1, addr_2: std_logic_vector(7 downto 0);
signal ready: std_logic;
signal bus_id: std_logic_vector(7 downto 0);
signal StopClock : boolean := FALSE;
begin
UUT :memory_controller
port map( clk => clk,
reset => reset,
bus_id => bus_id,
read_write => read_write,
burst => burst,
ready => ready,
oe => oe,
we => we,
addr_1 => addr_1,
addr_2 => addr_2);
clk_process: process
begin
while not StopClock loop
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end loop;
end process clk_process;
stim: process is
begin
reset <= '1', '0' after 50 ns;
bus_id <= "11110011";
wait for 5 ns;
read_write <= '0';
wait for 5 ns;
ready <= '1';
bus_id <= "11110011";
wait for 5 ns;
read_write <= '1';
assert (ready <='1' and burst <= '1')
report "Illegal state"
severity error;
assert (ready <= '1' and burst <='0')
report "Illegal state"
severity error;
wait for 5 ns;
ready <= '0';
wait for 5 ns;
burst <= '0';
wait for 5 ns;
ready <= '1';
wait for 5 ns;
burst <= '1';
wait for 5 ns;
ready <= '0';
wait for 5 ns;
ready <= '1';
wait for 5 ns;
ready <= '1';
end process;
end test;
configuration CFG_memory_controller of memory_controller_tb is
for test
for UUT : memory_controller
end for;
end for;
end;
当burst被断言时，它应该在ready断言时通过read1 read2 read3和read4（如当burst = 1时，它应该继续读取2，读取3，如果ready为1，则读取4）并且不能进入空闲状态如果重置在两者之间的任何时间变为 0。但它对我有用。如何更改程序以使其不依赖于重置？
此外，当地址重置为返回空闲状态时，地址不会重置为 0。当我尝试更改代码时，它说我试图从多个地方断言地址。
另外，我认为我的测试台写作技巧很糟糕，是否有任何规则或指导方针可以遵循，还是你必须为此培养一种直觉？
谢谢！