delay - 延迟 vhdl 中的信号

Question

我想在 vhdl 中将信号延迟几个周期，但是我在使用如何在 vhdl 中将信号延迟几个周期时遇到问题

我不需要注册信号吗？我的意思是，类似：

---

a_store and a_store_registered would be std_logic_vector(cycles_delayed-1 downto 0)

---

process(clk)
begin
    if rising_edge(clk) then
      a_store_registered <= a_store;
    end if;
end process;    
a_out <= a_store_registered(cycles_delayed-1);

process(a_store_registered, a)
begin    
      a_store <= a_store_registered(size-2 downto 0) & a;
end process;

---

Answer 1

您链接到的解决方案是rising_edge(clk)注册信号 - 使用限定符在进程内写入信号的行为会创建寄存器。

延迟线的一个更简单的实现可以在一行代码中实现（如果你想将高位复制到输出，再加上另一个）

a_store <= (a_store(a_store'high-1 downto 0) & a) when rising_edge(clk);
a_out <= a_store(a_store'high);

不知道为什么我在对链接问题的回答中没有提到这一点！

Answer 2

I am not sure why you are approaching the problem as you are; there is no need for a second process here. What is wrong with the method suggested in the linked question?

if rising_edge(clk) then
  a_store <= a_store(store'high-1 downto 0) & a;
  a_out <= a_store(a_store'high);
end if;

In this case your input is a and your output is a_out. If you want to make the delay longer, increase the size of a_store by resizing the signal declaration.

If you want to access the intermediate signal for other reasons, you could do this:

a_store <= a_store_registered(cycles_delayed-2 downto 0) & a;
process(clk)
begin
    if rising_edge(clk) then
      a_store_registered <= a_store;
    end if;
end process;    
a_out <= a_store_registered(cycles_delayed-1);

Answer 3

请记住，您可以使用该foo'delayed(N ns)属性或foo <= sig after N ns在模拟中。