最近,我在verilog中看到了一些D触发器RTL代码,如下所示:
module d_ff(
input d,
input clk,
input reset,
input we,
output q
);
always @(posedge clk) begin
if (~reset) begin
q <= 1'b0;
end
else if (we) begin
q <= d;
end
else begin
q <= q;
end
end
endmodule
声明q <= q;
有必要吗?