module A (
output A_OPORT_1
);
endmodule
module B (
input B_IPORT_1
);
endmodule
module TestBench;
wire A_to_B;
A A_inst (
.A_OPORT_1 (A_to_B)
);
B B_inst (
.B_IPORT_1 (A_to_B)
);
endmodule
这里基本上输出端口 A:A_inst:A_OPORT_1 连接到 B:B_inst:B_IPORT_1
如何使用 verilog PLI 检索该信息?例子赞赏。
我有一些代码可以获取端口并检索 highconn 并能够获取线/网 A_to_B。
但是,我无法使用 vpiPortInst 找出哪些端口连接到 A_To_B。我得到一个为空的迭代器。
vpiHandle high = vpi_handle(vpiHighConn, port);
vpi_printf(" High conndata type is %s\n",
vpi_get_str(vpiType, high));
vpi_printf(" High conndata Net type is %s\n",
vpi_get_str(vpiNetType, high));
vpi_printf(" High conndata Name is %s\n",
vpi_get_str(vpiFullName, high));
vpiHandle iter = vpi_iterate(vpiPortInst,high);
vpiHandle p2ref;
if (iter == NULL)
{
vpi_printf(" Port Iterator is null\n");
}
输出/输出:
High conndata type is vpiNet
High conndata Net type is vpiWire
High conndata Name is $unit::A_to_B
Port Iterator is null