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我们正在尝试写入 Terasic DE1 FPGA 板上的 SRAM 芯片，但是我们遇到了与三态控制有关的错误。错误如下：

Error (10137): Verilog HDL Procedural Assignment error at inputOutputControl.v(32): object "SRAM_DATA" on left-hand side of assignment must have a variable data type
Error (10137): Verilog HDL Procedural Assignment error at inputOutputControl.v(33): object "SRAM_DATA" on left-hand side of assignment must have a variable data type
Error (10219): Verilog HDL Continuous Assignment error at inputOutputControl.v(52): object "SRAM_LB_N" on left-hand side of assignment must have a net type
Error (10219): Verilog HDL Continuous Assignment error at inputOutputControl.v(53): object "SRAM_UB_N" on left-hand side of assignment must have a net type

我们遇到问题的模块如下所示，任何人都可以阐明我们如何使其工作吗？

module ram_writer(
input               CLK,
input               RESET_N,
input               V_PORCH_EN,
input               LOGIC_WE_N,
input               LOGIC_CE_N,
input        [17:0] LOGIC_WRITE_ADDRESS,        
input        [15:0] LOGIC_WRITE_DATA,
input               VGA_OE_N,
input               VGA_CE_N,
input        [17:0] VGA_READ_ADDRESS,       
output       [15:0] VGA_READ_DATA,
output  reg         SRAM_OE_N,
output  reg         SRAM_WE_N,
output  reg         SRAM_CE_N,
output  reg         SRAM_LB_N,
output  reg         SRAM_UB_N,
output  reg  [17:0] SRAM_ADDRESS,       
inout   wire [15:0] SRAM_DATA   
);

reg [15:0] writeData;

always @(posedge CLK)
begin
   writeData       <= LOGIC_WRITE_DATA;                    
   VGA_READ_DATA   <= SRAM_DATA;
end

always @((posedge LOGIC_WE_N or writeData))
begin
   if( LOGIC_WE_N == 1) SRAM_DATA = 16'bZ;
   else SRAM_DATA = writeData; 
end

always @(posedge CLK)
begin
   if(V_PORCH_EN == 1) begin
   SRAM_ADDRESS <= LOGIC_WRITE_ADDRESS;
   SRAM_CE_N    <= LOGIC_CE_N;
   SRAM_WE_N    <= LOGIC_WE_N; 
   SRAM_OE_N    <= 1;
   end 
   else begin
   SRAM_ADDRESS <= VGA_READ_ADDRESS;
   SRAM_CE_N    <= VGA_CE_N;
   SRAM_OE_N    <= VGA_OE_N; 
   SRAM_WE_N    <= 1;
   end 
end

assign SRAM_LB_N = 0; 
assign SRAM_UB_N = 0; 

endmodule
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1 回答 1

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我认为这：

Error (10137): Verilog HDL Procedural Assignment error at inputOutputControl.v(32): object "SRAM_DATA" on left-hand side of assignment must have a variable data type
Error (10137): Verilog HDL Procedural Assignment error at inputOutputControl.v(33): object "SRAM_DATA" on left-hand side of assignment must have a variable data type

参考这个：

if( LOGIC_WE_N == 1) SRAM_DATA = 16'bZ;
else SRAM_DATA = writeData;

'wire' 数据类型没有内存，因此您必须使用连续分配来分配它，而不是始终块。

反之在这里：

assign SRAM_LB_N = 0; 
assign SRAM_UB_N = 0;

您不能通过连续分配来分配 reg 类型，它必须在 always 块中分配。

于 2012-04-17T21:58:14.040 回答