我有一个带有计数器的伪随机数生成器的问题,以检查我是否正在处理不可约多项式。生成器工作正常,但如果我尝试将其用作子模块,则计数器不会。任何想法 ??
-- x^6 + x^5 + x^3 + x^2 + 1
Library IEEE;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity EPZG is
port (CLK: in std_logic;
EQ: out bit_vector(5 downto 0);
A : out bit );
end EPZG;
architecture behaviour of EPZG is
component Counter is port ( CLK, RESET : in std_logic;
result: out bit_vector(5 downto 0));
end component;
signal SZ: bit;
signal SEQ : bit_vector(5 downto 0);
signal CNT_RESET : std_logic;
signal CNT_RESULT : bit_vector(5 downto 0);
begin
SZ <= '1';
PZG : process(CLK)
begin
CNT_RESET <= '1';
if (CLK'event and CLK ='1') then
SEQ(0) <= SZ xor SEQ(5);
SEQ(1) <= SEQ(0);
SEQ(2) <= SEQ(1) xor SEQ(5);
SEQ(3) <= SEQ(2) xor SEQ(5);
SEQ(4) <= SEQ(3);
SEQ(5) <= SEQ(4) xor SEQ(5);
end if;
end process PZG;
EQ <= SEQ;
CNT: Counter port map ( CLK , RESET =>CNT_RESET,result =>CNT_RESULT);
end behaviour;
计数器代码
图书馆 IEEE;使用 IEEE.STD_LOGIC_1164.ALL;使用 ieee.std_logic_unsigned.all;
entity Counter is port (CLK, RESET : in std_logic; result: out bit_vector(5 downto 0)); end Counter; architecture BEHAVIOUR of Counter is signal pre_counter: std_logic_vector(5 downto 0); begin REG : process(CLK, RESET) begin if(CLK'event and CLK = '1') then if (RESET = '0') then pre_counter <= (others =>'0'); else pre_counter <= pre_counter +1 ; end if; end if; end process; result <= To_bitvector (pre_counter); end BEHAVIOUR;