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I'm having a hard time understanding the way flip-flops actually flip states and wondering why is it such a design commonly used, when simpler design could suffice, from my current opinion.

I'm hoping that after showing you my version of a latch diagram, someone could point out the flaws and that may help me understand why a flip-flop latch is better.

I was reading a book and bumped into some "general" form of latch: https://i.imgur.com/nkldf4u.png (sorry, I don't have the reputation insert images)

I've been on it for about 2 hours trying to truly grasp the mechanism. Seeing that I can't do it, I've draw my version of a latch:

https://i.imgur.com/fFgpNzR.png

The blue diagram, the one from the book, is harder to follow because some gates will switch 2 times when the inputs switches once, because as the output is tunneled back as input to the same gate, the output may change base on its previous value.

My version of the diagram, the one in black, uses a more programmable approach. I take the current state C and decide if it differs from the input state and output it into A. I use A value in an AND gate with the enable wire to decide if both criteria is met and put it in B. Finally, I'm using a XOR to change the state and output as C.

I'm hoping someone can tell me why is this bad, what I haven't taken into consideration or why a more complex mechanism is needed.

Thank you in anticipation.

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据我所知，您的闩锁实现应该可以工作。

然而，低级数字设计不仅仅是门数。在实际电路中，并非所有门都是平等的，因为这些门的实际实现可能会比其他门更“昂贵”（通常以面积/晶体管数量和布线复杂度来衡量）。对于典型的 CMOS 实现，NAND 门非常便宜（两个输入 NAND 只有 4 个晶体管），因此许多原语使用 NAND（或 NOR）作为更复杂设计的构建块。XOR 通常是一个更复杂的门实现，我见过的大多数 CMOS 实现使用 8 个晶体管。如果不经过和优化您的设计，可能需要至少 20 个或更多的晶体管来实现，而教科书中的锁存器设计只需要 16 个（每存储位节省 20% 以上的面积，这非常重要）。除了晶体管数量之外，这里还有很多东西在起作用。在实际进行和实施设计时，诸如晶体管尺寸、布线和走线尺寸、电源考虑因素和毛刺保护之类的东西，所以即使是这个简单的分析也不完整，并且可能缺少教科书实施与您的实施的原因（反之亦然）。

异步时序逻辑（这就是锁存器/触发器的实现）可能很难理解，这就是为什么大多数电路使用更高级别的构造并将这些细节视为黑匣子的原因（并且它还创建了一个很好的抽象，其中实际实现并不重要所以只要保留该元素的属性）。

于 2019-05-31T17:37:29.383 回答