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在使用 ghdl vhdl 模拟器进行编译时，有什么想法会导致此错误吗？

$ ghdl -a /common_pkg.vhd
./common_sim_pkg.vhd:2:14: file std_logic_1164.v93 has changed and must be reanalysed

common_pkg.vhd 是：

library ieee;
use     ieee.std_logic_1164.all;

package common_pkg is

  component block1 is
    port (
      port1  : out std_logic_vector(13 downto 0);
      port2  : in    std_logic;
      port3  : in    std_logic;
      port4  : in    std_logic
      );
  end component;

  component block2 is
    port(
      port1 : in    std_logic_vector(11 downto 0);
      port2 : in    std_logic_vector(11 downto 0);
      port3 : in    std_logic_vector(11 downto 0);
      port4 : in    std_logic_vector(11 downto 0);
      port5 : in    std_logic_vector(11 downto 0);
      port6 : in    std_logic_vector(11 downto 0);
      port7 : in    std_logic_vector(11 downto 0);
      port8 : in    std_logic_vector(11 downto 0);

      port9  :   out std_logic;
      port10 : in    std_logic;
      port11 : in    std_logic;
      port12 : in    std_logic
      );
  end component;

end package;

这是ghdl版本：

$ ghdl -v
GHDL 0.29.1 (20100301) [Sokcho edition]
 Compiled with GNAT Version: GPL 2009 (20090519)
 mcode code generator
Written by Tristan Gingold.

Copyright (C) 2003 - 2010 Tristan Gingold.
GHDL is free software, covered by the GNU General Public License.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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