syntax - 使用 Case 语句的 JK 触发器的 VHDL 程序

Question

library ieee;
use ieee. std_logic_1164.all;
 entity JKFF is
PORT( j,k,clock: in std_logic;
q,qbar: out std_logic);
end JKFF;
Architecture behavioral of JKFF is
signal jk : std_logic_vector(1 downto 0);
signal temp : std logic;
begin

process(clock,j,r)

begin
jk <= j & k;
if(clock= '1' and clock'event) then
 case (jk) is
   when "00" => temp<= temp;
   when "01" => temp <= '0';
   when "10" => temp <= '1';
   when "11" => not temp;
   when others => temp <= 'X'
end case;
end process;
q <= temp;
qbar <= not temp;

end behavioral;

当我使用 ghdl 编译这个程序时，它显示错误“何时”是预期的，而不是“不是”。请帮我找出这段代码的问题。

Answer 1

you forgot these things:

1)when "11" => not temp; to when "11" => temp <= not temp;

2)when others => temp <= 'X' must have semicolon at the end when others => temp <='X';

3)you missed end ifat the end of the if

4)process sensitivity list contains a signal named ‘r’ which is undeclared

I’ve left out the signal j and k from the process because all the code you execute in the if statement is conditioned only by the clock, so there is no need to execute the process when j and k change their value and the clock isn’t on rising edge.

library ieee;
use ieee. std_logic_1164.all;
 entity JKFF is
PORT( j,k,clock: in std_logic;
q,qbar: out std_logic);
end JKFF;
Architecture behavioral of JKFF is
signal jk : std_logic_vector(1 downto 0);
signal temp : std logic;
begin

process(clock)

begin
jk <= j & k;
if(clock= '1' and clock'event) then
   case (jk) is
     when "00" => temp<= temp;
     when "01" => temp <= '0';
     when "10" => temp <= '1';
     when "11" => temp <= not temp;
     when others => temp <= 'X';
    end case;
end if;
end process;
q <= temp;
qbar <= not temp;

end behavioral;