我正在按照下面的python代码在verilog中实现Cholesky分解
def cholesky(A):
n = len(A)
L = [[0.0] * n for i in xrange(n)]
for i in xrange(n):
for j in xrange(i+1):
tmp_sum = sum(L[i][k] * L[j][k] for k in xrange(j))
if (i == j): # Diagonal element
L[i][j] = sqrt(A[i][i] - tmp_sum)
else:
L[i][j] = (1.0/L[j][j] * (A[i][j] - tmp_sum))
return L
我尝试用 3x3 输入大小做一个简单的。由于它需要除法和平方根，我还使用标准方法（从互联网复制并进行了一些修改）编写了一个除法，并使用巴比伦方法（牛顿方法的一种变体）编写了一个 sqrt。他们来了：
分配
module Div(in1, in2, out);
input [23:0] in1, in2;
output reg [23:0] out;
// reg [23:0] remainder;
reg [47:0] scaled_divider, temp_remainder, temp_result;
integer i;
always @ (in1 or in2) begin
scaled_divider = {1'b0, in2, 23'h0};
temp_remainder = {24'h0, in1};
for (i=0; i<24; i=i+1) begin
temp_result = temp_remainder - scaled_divider;
if (temp_result[47-i]) begin // Negative result, quotient set to '0'
out[23-i] = 1'b0;
end else begin
out[23-i] = 1'b1;
temp_remainder = temp_result;
end
scaled_divider = scaled_divider >> 1;
end
// remainder = temp_remainder[23:0];
end
endmodule
平方
module Sqrt_newton(in, out);
// 3 iterations
input [23:0] in;
output reg [23:0] out;
Div div1(in, out, tmp_inout1);
Div div2(in, tmp_inout2, tmp_inout3);
Div div3(in, tmp_inout4, tmp_inout5);
always @ (in)
begin
out[0] = 1'b1;
out[1] = 1'b1;
out[2] = 1'b1;
out[3] = 1'b1;
out[4] = 1'b1;
out[5] = 1'b1;
out[6] = 1'b1;
out[7] = 1'b1;
tmp_inout2 = (out + tmp_inout1) >> 1;
tmp_inout4 = (tmp_inout2 + tmp_inout3) >> 1;
out = (tmp_inout4 + tmp_inout5) >> 1;
end
endmodule
这是我的 3x3 cholesky 分解代码：
module cholesky_template(clk, rst, g_input, e_input, o);
input clk, rst;
input [143:0] g_input;
input e_input;
output [215:0] o;
reg [23:0] L [0:2][0:2];
reg [23:0] A [0:2][0:2] ;
assign o = {
L[0][0], L[0][1], L[0][2],
L[1][0], L[1][1], L[1][2],
L[2][0], L[2][1], L[2][2]
};
reg [23:0] tmp_A00_minus_sum;
reg [23:0] tmp_A11_minus_sum;
reg [23:0] tmp_A22_minus_sum
reg [23:0] tmp_A10_minus_sum;
reg [23:0] tmp_A20_minus_sum;
reg [23:0] tmp_A21_minus_sum;
reg [23:0] div_1_L00;
reg [23:0] div_1_L11;
Sqrt sqrt0(tmp_A00_minus_sum, L[0][0]);
Div div0(1'b1, L[0][0], div_1_L00);
Sqrt sqrt1(tmp_A11_minus_sum, L[1][1]);
Div div1(1'b1, L[1][1], div_1_L11);
Sqrt sqrt2(tmp_A22_minus_sum, L[2][2]);
always @ (posedge clk or posedge rst) begin
if (rst)
L[0][0] = 1'b0;
L[0][1] = 1'b0;
L[0][2] = 1'b0;
L[1][0] = 1'b0;
L[1][1] = 1'b0;
L[1][2] = 1'b0;
L[2][0] = 1'b0;
L[2][1] = 1'b0;
L[2][2] = 1'b0;
tmp_sum = 1'b0;
A[0][0] ={8'b00000000, g_input[15:0]};
A[0][1] =24'b0; // will not be used
A[0][2] =24'b0; // will not be used
A[1][0] ={8'b00000000, g_input[63:48]};
A[1][1] ={8'b00000000, g_input[79:64]};
A[1][2] =24'b0; // will not be used
A[2][0] ={8'b00000000, g_input[111:96]};
A[2][1] ={8'b00000000, g_input[127:112]};
A[2][2] ={8'b00000000, g_input[143:128]};
end else begin
tmp_A00_minus_sum = A[0][0] - tmp_sum;
tmp_A10_minus_sum = A[1][0] - tmp_sum;
L[1][0] = div_1_L00 * tmp_A10_minus_sum;
tmp_sum = tmp_sum + L[1][0] * L[1][0];
tmp_A11_minus_sum = A[1][1] - tmp_sum;
tmp_A20_minus_sum = A[2][0] - tmp_sum;
L[2][0] = div_1_L00 * tmp_A20_minus_sum;
tmp_sum = tmp_sum + L[2][0] * L[1][0];
tmp_A21_minus_sum = A[2][1] - tmp_sum;
L[2][1] = div_1_L11 * tmp_A21_minus_sum;
tmp_sum = tmp_sum + L[2][0] * L[2][0];
tmp_sum = tmp_sum + L[2][1] * L[2][1];
tmp_A22_minus_sum = A[2][2] - tmp_sum;
end
end
endmodule
对代码的一些解释：我没有使用 for 循环，所以我将它们展开为tmp_A10_minus_sum = A[1][0] - tmp_sum;. 映射到 python 代码应该相当容易。之前插入 8 个零的原因A是我会尝试将代码“升级”为使用 24 位，以便它可以更准确。这不是问题。
三态总线警告
问题是当我使用 Synopsys DC 编译它时，它会输出如下警告：
“警告：在设计‘cholesky_template’中，三态总线‘tmp_A00_minus_sum[23]’具有非三态驱动程序‘tmp_A00_minus_sum_reg[23]/Q’。(LINT-34)”
这是 DC 对 LINT-34 的描述：
NAME LINT-34（警告）在设计“%s”中，三态总线“%s”具有非三态驱动程序“%s”。
描述 Synopsys 库包含对组件上的三态驱动引脚的描述。如果网络由至少一个具有三态属性的引脚驱动，则 Synopsys 工具将其分类为三态网络。通常，如果此类网络上有多个驱动器，则假定所有驱动引脚都应为三态驱动器，以正确操作三态总线。此警告消息指示至少一个非三态驱动程序出现在三态网络上的情况。
WHAT_NEXT 验证这是您对给定网络的预期。如果消息中指定的非三态驱动引脚确实在您的 ASIC 技术中的三态驱动上，请验证技术库描述是否正确。
为什么设计中有三态属性？我该如何纠正它们？
目标库不包含寄存器的替代品
这是我收到的另一个警告，例如：
警告：目标库不包含寄存器“A_reg[1][0][7]”（FFGEN）的替代品。(TRANS-4)
这是我的库代码，我想知道这是否与三态总线警告有关？如果是这样，是否有任何参考来设计适当的细胞？
library(HML){
cell(AND) {
area: 6;
pin(A) {
direction: input;
capacitance: 1;
}
pin(B) {
direction: input;
capacitance: 1;
}
pin(Z) {
direction: output;
function: "A B";
timing() {
intrinsic_rise: 0.48;
intrinsic_fall: 0.77;
rise_resistance: 0.1443;
fall_resistance: 0.0523;
slope_rise: 0.0;
slope_fall: 0.0;
related_pin: "A";
}
timing() {
intrinsic_rise: 0.48;
intrinsic_fall: 0.77;
rise_resistance: 0.1443;
fall_resistance: 0.0523;
slope_rise: 0.0;
slope_fall: 0.0;
related_pin: "B";
}
}
}
cell(OR) {
area: 6;
pin(A) {
direction: input;
capacitance: 1;
}
pin(B) {
direction: input;
capacitance: 1;
}
pin(Z) {
direction: output;
function: "A+B";
timing() {
intrinsic_rise: 0.28;
intrinsic_fall: 0.85;
rise_resistance: 0.1443;
fall_resistance: 0.0589;
slope_rise: 0.0;
slope_fall: 0.0;
related_pin: "A";
}
timing() {
intrinsic_rise: 0.28;
intrinsic_fall: 0.85;
rise_resistance: 0.1443;
fall_resistance: 0.0589;
slope_rise: 0.0;
slope_fall: 0.0;
related_pin: "B";
}
}
}
cell(XOR) {
area: 0;
pin(A) {
direction: input;
capacitance: 1;
}
pin(B) {
direction: input;
capacitance: 1
}
pin(Z) {
direction: output;
function: "A^B";
timing() {
intrinsic_rise: 0.28;
intrinsic_fall: 0.85;
rise_resistance: 0.1443;
fall_resistance: 0.0589;
slope_rise: 0.0;
slope_fall: 0.0;
related_pin: "A";
}
timing() {
intrinsic_rise: 0.28;
intrinsic_fall: 0.85;
rise_resistance: 0.1443;
fall_resistance: 0.0589;
slope_rise: 0.0;
slope_fall: 0.0;
related_pin: "B";
}
}
}
cell(NAND) {
area: 6;
pin(A) {
direction: input;
capacitance: 1;
}
pin(B) {
direction: input;
capacitance: 1
}
pin(Z) {
direction: output;
function: "(A B)'";
timing() {
intrinsic_rise: 0.28;
intrinsic_fall: 0.85;
rise_resistance: 0.1443;
fall_resistance: 0.0589;
slope_rise: 0.0;
slope_fall: 0.0;
related_pin: "A";
}
timing() {
intrinsic_rise: 0.28;
intrinsic_fall: 0.85;
rise_resistance: 0.1443;
fall_resistance: 0.0589;
slope_rise: 0.0;
slope_fall: 0.0;
related_pin: "B";
}
}
}
cell(NOR) {
area: 6;
pin(A) {
direction: input;
capacitance: 1;
}
pin(B) {
direction: input;
capacitance: 1
}
pin(Z) {
direction: output;
function: "(A+B)'";
timing() {
intrinsic_rise: 0.28;
intrinsic_fall: 0.85;
rise_resistance: 0.1443;
fall_resistance: 0.0589;
slope_rise: 0.0;
slope_fall: 0.0;
related_pin: "A";
}
timing() {
intrinsic_rise: 0.28;
intrinsic_fall: 0.85;
rise_resistance: 0.1443;
fall_resistance: 0.0589;
slope_rise: 0.0;
slope_fall: 0.0;
related_pin: "B";
}
}
}
cell(XNOR) {
area: 6;
pin(A) {
direction: input;
capacitance: 1;
}
pin(B) {
direction: input;
capacitance: 1
}
pin(Z) {
direction: output;
function: "(A^B)'";
timing() {
intrinsic_rise: 0.28;
intrinsic_fall: 0.85;
rise_resistance: 0.1443;
fall_resistance: 0.0589;
slope_rise: 0.0;
slope_fall: 0.0;
related_pin: "A";
}
timing() {
intrinsic_rise: 0.28;
intrinsic_fall: 0.85;
rise_resistance: 0.1443;
fall_resistance: 0.0589;
slope_rise: 0.0;
slope_fall: 0.0;
related_pin: "B";
}
}
}
cell(DFF) {
area : 9;
pin(D) {
direction : input;
capacitance : 1;
timing() {
timing_type : setup_rising;
intrinsic_rise : 0.85;
intrinsic_fall : 0.85;
related_pin : "CLK";
}
timing() {
timing_type : hold_rising;
intrinsic_rise : 0.4;
intrinsic_fall : 0.4;
related_pin : "CLK";
}
}
pin(I) {
direction : input;
capacitance : 1;
timing() {
timing_type : setup_rising;
intrinsic_rise : 0.85;
intrinsic_fall : 0.85;
related_pin : "CLK";
}
timing() {
timing_type : hold_rising;
intrinsic_rise : 0.4;
intrinsic_fall : 0.4;
related_pin : "CLK";
}
}
pin(CLK) {
direction : input;
capacitance : 1;
}
pin(RST) {
direction : input;
capacitance : 2;
}
ff("IQ", "IQN") {
next_state : "D";
clocked_on : "CLK";
clear : "RST (I')";
preset: "RST I";
clear_preset_var1: L;
clear_preset_var2: H;
}
pin(Q) {
direction : output;
function : "IQ";
internal_node : "Q";
timing() {
timing_type : rising_edge;
intrinsic_rise : 1.19;
intrinsic_fall : 1.37;
rise_resistance : 0.1458;
fall_resistance : 0.0523;
related_pin : "CLK";
}
timing() {
timing_type : clear;
timing_sense : positive_unate;
intrinsic_fall : 1.29;
fall_resistance : 0.0516;
related_pin : "RST";
}
timing() {
timing_type : preset;
timing_sense : positive_unate;
intrinsic_fall : 1.29;
fall_resistance : 0.0516;
related_pin : "I";
}
}
}
cell(IV){
area:0;
cell_footprint : "iv";
pin(A) {
direction: input;
capacitance: 1;
}
pin(Z) {
direction: output;
function : "A'";
timing() {
intrinsic_rise : 0.38;
intrinsic_fall : 0.15;
rise_resistance : 0.1443;
fall_resistance : 0.0589;
slope_rise : 0.0;
slope_fall : 0.0;
related_pin : "A";
}
}
}
}
抱歉发了很长的帖子。我希望我清楚地问了我的问题。